[maemo-developers] [maemo-developers] gstreamer launcher (proper video sink?)

From: klaus at rotters.de klaus at rotters.de
Date: Wed Apr 26 23:33:48 EEST 2006
Am 26 Apr 2006 um 14:47 hat Frantisek Dufka geschrieben:
> True. Well, as for the measuring, I only know my Tungsten T2 (OMAP 
> 1510,168Mhz) can play 320x240, 25FPS, 300Kbits mp4 videos better than my 
> N770. And TCPMP (palmos video player) uses ARM core only. So I suppose 
> even ARM4 core is good enough. I guess 250Mhz ARM5 together with DSP 
> helping with decoding audio (and maybe some video step - blitting with 
> color space conversion?) could do much better.

The OMAP 1510 has a internal Framebuffer - the framebuffer in the 
N770 is external (I think) and has to be accessed via the 16-bit 
memory bus. There are internal caches, but program code and the 
data has also to be transported via the 16-bit memory bus. Maybe 
that's the bottle neck. The OMAP has also just a 16-bit bus, but has a 
internal frame buffer, which may be accessed faster without blocking 
the external 16-bit bus. This the dsp and ARM cpu core share the 
same memory bus. The cache sizes and built-in memories of the 
OMAP 1710 cpu are:

TMS320C55x DSP core subsystem

    * Up to 220 MHz (maximum frequency)
    * 32K x 16-bit on-chip dual-access RAM (DARAM) (64 KB)
    * 48K x 16-bit on-chip single-access RAM (SARAM) (96 KB)
    * 24 KB I-cache
    * One/two instructions executed per cycle
    * Video hardware accelerators for DCT, iDCT, pixel interpolation, 
and motion estimation for video compression

ARM926TEJ core subsystem

    * Up to 220 MHz ARM926TEJ V5 architecture (maximum 
    * 32KB I-cache; 16KB D-cache
    * Java acceleration
    * Support for 32-bit and 16-bit (thumb mode) instruction sets
    * Data and program MMUs
    * Two 64-entry translation look-aside buffers (TLBs) for MMUs
    * 17-word write buffer

Since the DSP has hardware accelerators for (i)DCT etc I really think it 
should perform faster than the ARM cpu. I also think (but I am not 
shure) that TIs 320C55x DSP has a 16 bit opcode length whereas the 
ARM uses 32 bit (not in thumb mode), so the DSP core should be able 
to store more program code in its 24 KB instruction cache than the 
ARM core.

Further it would be interesting which MPEG4 decoder the N770 uses, 
there are a couple of implementations for 320C55x dsps around, more 
or less optimzied.

 Klaus Rotter * klaus <at> rotters <dot> de * www.rotters.de

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