[maemo-developers] ARM MMU questions

[From: Frantisek Dufka]

Simon Pickering wrote:
> Hello all,
> 
> I'm looking to share the framebuffer between the ARM CPU and DSP and
> therefore would like to ask a few questions about the ARM MMU and in
> particular TLBs.

Most probably it is related to DSP MMU not ARM MMU but I am not sure. 
Until now I thought TLB (translation look-aside buffer) is dynamic thing 
you mostly don't care about just like L2 or L1 CPU cache (Well unless 
you read LWN of course :-) see 
http://lwn.net/SubscriberLink/255364/65f972b0422f379b/ ).

Since the message "TLB full" did not make sense to me at all I did a 
google check and got this
http://focus.ti.com/lit/an/swpa038/swpa038.pdf

"When table walking is enabled, TLB entries are automatically written by 
the table walking logic. Alternatively, entries can also be manually 
written by the user. This is done to ensure that the time-critical data 
accesses execute as fast as possible. Such user-defined entries are 
typically locked to prevent them from being overwritten subsequently. "

Page 16 "Programming the DSP MMU

The DSP MMU can be programmed in two ways: by building translation 
tables or by writing all
required entries directly into the TLB. A mix of these two ways is also 
possible. In that case,
translation tables are used but some of the most time-critical 
translations are preloaded into the
TLB."

So it looks like DSP TLB is set up manually for fast access and indeed 
it may be full.


> So it appears that I'm running out of TLBs in the ARM MMU.

I think TLB on main (ARM) cpu is too precious to be locked in this way 
since it is needed for every access to memory by every process. I guess 
it really may be DSP MMU where it make more sense.


> It's interesting that the 770 has a mapped framebuffer. I wonder how it
> gets away with doing this while the N800 can't (if it's not by using a
> larger page size)?

770 has framebuffer mapped for DSP because there are video codecs 
implemented as DSP tasks. This is no longer true with N800 so mapping 
for DSP makes little sense. With N800 some (or all? video one at least) 
planes are even mapped to SRAM not normal SDRAM like with 770 so maybe 
it is even not accessible by DSP (not sure about this limitation at all).

I hope all this is not completely wrong and can help you but I don't 
know how to solve this. Maybe the set of DSP tasks on N800 are coded to 
use TLB fully since framebuffer acces is not needed. Still the rest free 
TLB entries may be enough if it is possible to use them in dynamic way 
but it will be slower. That's how I understand it.

Frantisek